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ADuC7060
Table 38. ADCSTA MMR Bit Designations
Bit
15
14
13
12
11 to 7
6
5
4
3
2
1
0
Name
ADCCALSTA
ADC1CERR
ADC0CERR
ADC0ATHEX
ADC0THEX
ADC0OVR
ADC1RDY
ADC0RDY
Description
ADC calibration status.
This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed.
This bit is cleared after ADCMDE is written to.
Not used.
This bit is reserved for future functionality
Auxiliary ADC conversion error.
This bit is set automatically in hardware to indicate that an auxiliary ADC conversion overrange or underrange has
occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange
error) in this case.
This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
Primary ADC conversion error.
This bit is set automatically in hardware to indicate that a primary ADC conversion overrange or underrange has
occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange
error) in this case.
This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 accumulator comparator threshold exceeded.
This bit is set when the ADC0 accumulator value in ADC0ACC exceeds the threshold value programmed in the
ADC0 comparator threshold register, ADCOATH.
This bit is cleared when the value in ADC0ATH does not exceed the value in ADC0ATH.
Not used. This bit is reserved for future functionality and should not be monitored by user code.
Primary channel ADC comparator threshold. This bit is valid only if the primary channel ADC comparator is enabled
via the ADCCFG MMR.
This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in
the ADC0TH MMR. If the ADC threshold counter is used (ADC0RCR), this bit is set only when the specified number
of primary ADC conversions equals the value in the ADC0THV MMR.
Otherwise, this bit is clear.
Primary channel ADC overrange bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is set
by hardware if the primary ADC input is grossly (>30% approximate) overrange. This bit is updated every 125 μs.
After it is set, this bit can be cleared only by software when ADCCFG[2] is cleared to disable the function, or the
ADC gain is changed via the ADC0CON MMR.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Auxiliary ADC result ready bit.
If the auxiliary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC1DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC1DAT followed by reading ADC0DAT. ADC0DAT must be read to clear this bit, even
if the primary ADC is not enabled.
Primary ADC result ready bit.
If the primary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC0DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC0DAT.
Rev. 0 | Page 37 of 100
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